rtl-design jobs in San Diego

Senior ASIC engineer responsible for defining, modeling, designing (digital and/or analog), optimizing, verifying, validating, implementing, and documenting IP blocks and SoCs for high-performance, low-power products. Design and architecture duties span RTL-to-GDS flow, circuit specifications, logic design, system simulation, timing, power analysis, and design verification.…See more Requires 2+ years of ASIC design/verification experience (or equivalent with advanced degree) and proficiency with EDA tools, scripting, and design verification methodologies. Works independently with cross-functional collaboration and produces detailed technical documentation.

Senior Technical Program Manager leading ASIC/SOC development programs from architecture through post-silicon validation. Manages cross-functional engineering teams across pre-silicon phases (architecture, RTL design, verification, FPGA prototyping, physical design, tapeout) and post-silicon phases (silicon bring-up, functional validation, NPI).…See more Drives project execution, technical trade-offs, and coordination with internal teams, foundries, and external partners to meet power, performance, schedule, cost, and quality requirements. Requires 7+ years managing ASIC teams, 5+ years technical program management, and 3+ years software development experience.

As an ASIC RTL Design Engineer, you will define, model, design, optimize, verify, and validate IP blocks and SoCs for high-performance, low-power products. You will assist in creating architectures, circuit specifications, and logic designs based on system-level requirements, and collaborate with cross-functional teams to develop implementation strategies.…See more The role involves using EDA tools and RTL-to-GDS flows to execute design and supporting the evaluation of process flow from synthesis through place-and-route. You will work under supervision on tasks requiring multiple steps, planning, and problem-solving to deliver technical documentation for ASIC projects.

Design and develop performance modeling platforms and tools for Qualcomm's AI/ML hardware accelerators targeting cloud data server applications. Analyze and optimize LLM and AI workloads on SoC architectures, working across hardware architecture, DDR memory controllers, NoC design, and compiler frameworks.…See more Collaborate with multi-disciplinary hardware and systems engineers to find optimal architecture tradeoffs and improve performance and power efficiency. Apply deep expertise in AI workloads, ML frameworks, computer architecture, and RTL design/verification to build systems that validate LLMs and complex ML networks.

SoC Design and Integration Engineer at Qualcomm responsible for RTL design, architecture, and integration of high-performance ASICs for data center and AI applications. The role involves hands-on design and verification of complex chips, system simulation, large-scale design integration, and collaboration with cross-functional teams.…See more Candidates should have proven ASIC/FPGA design experience, knowledge of server/data center protocols, and expertise in arithmetic or machine-learning IP design. The position also values scripting, process automation, and the ability to identify flow improvements and provide silicon learnings feedback.

Staff Machine Learning Engineer to drive AI/ML-based automation across Qualcomm's Automotive SoC Cybersecurity and Safety engineering. The role focuses on building intelligent, scalable solutions using LLMs, GenAI, and agentic AI systems to streamline cybersecurity workflows, functional safety processes, and silicon verification.…See more Responsibilities include designing end-to-end ML pipelines, developing document-understanding and review-automation systems, and applying AI to security analysis and compliance monitoring across the product development lifecycle. Required: strong ML/AI background, Python or C++ proficiency, production ML experience; preferred: knowledge of automotive standards (ISO/SAE 21434, ISO 26262), hardware security, or RTL/verification workflows.

As an ASIC Digital Design Engineer, you will define, model, design, optimize, verify, and validate IP blocks and SoCs for high-performance, low-power memory subsystems (HBM, LPDDR). You'll work with cross-functional teams to develop architectures, circuit specifications, and logic designs based on system requirements, using EDA tools to execute the RTL-to-GDS flow and custom circuit design workflows.…See more Responsibilities include creating system simulations, evaluating implementation strategies, and documenting technical specifications for ASIC projects.

Design RTL for high-performance Hexagon/NPU processor cores used in mobile SoCs, servers, IoT, and automotive applications. Work across the full ASIC design flow from RTL through GDS2, collaborating with architecture, physical design, and verification teams on timing closure, power optimization, and area reduction.…See more Develop SystemVerilog RTL, run frontend design tools (linting, CDC, LEC, CLP), and support hardware integration and design verification. Requires 2+ years of practical RTL development experience with microprocessor design knowledge.

Staff Engineer role focused on CPU design, RTL development, and physical design for next-generation high-performance, low-power SoCs. Responsibilities span microarchitecture definition, Verilog/SystemVerilog RTL coding, synthesis, physical implementation (floorplanning, placement, routing, timing closure), and PPA optimization.…See more Will collaborate across architecture, verification, DFT, and post-silicon teams, and develop automation scripts in Python, Tcl, Perl, or Shell. Requires 4–10 years in ASIC/SoC, CPU, RTL, or physical design, strong digital design fundamentals, and hands-on experience with CPU microarchitecture and design closure flows.

Qualcomm seeks a Staff Machine Learning Engineer to design and deploy AI/ML-based automation solutions for automotive cybersecurity and functional safety engineering workflows. The role involves building intelligent systems for document understanding, compliance automation, and engineering productivity, leveraging LLMs, GenAI, and agentic AI frameworks.…See more You will develop scalable end-to-end automation pipelines, contribute to knowledge systems and RAG platforms, and apply ML to security analysis and process optimization across the full product development lifecycle. The ideal candidate has 5+ years of ML/AI experience, strong programming skills in Python or C++, and familiarity with automotive cybersecurity standards such as ISO/SAE 21434.

As a NoC Interconnect Design Engineer and Architect at Qualcomm, you will define, model, design, optimize, and verify network-on-chip IP blocks and SoCs for high-performance, low-power products. You will create architectures and circuit specifications based on system requirements, support the RTL-to-GDS implementation flow, and collaborate with cross-functional teams to meet customer needs.…See more The role requires hands-on use of EDA tools (RTL synthesis, place-and-route, timing/power analysis, and custom design tools like Virtuoso) and technical documentation. You will work under supervision on digital and/or analog design tasks that span from high-level specification through physical implementation.

Lead Arm's SoC interconnect technology team as a senior architect with 15+ years of experience designing large-scale SoCs. Own performance modeling, microarchitecture, RTL design, and verification strategy for interconnect IP; drive adoption of industry standards (AMBA AXI/ACE/CHI, etc.) across CPU, GPU, NPU, and memory subsystems.…See more Mentor a team of architects and engineers while leading complex projects to tape-out, with expertise in coherent protocols, cache coherency, latency/bandwidth/power optimization, and system-level debug.

Define and architect next-generation SoC infrastructure hardware components including interconnect (NoC), system cache, memory controllers, and system MMU for Qualcomm SoCs. The role requires deep expertise in multi-die/chiplet architectures, industry-standard protocols (PCIe, CXL, USB, UFS, MIPI, UCIe), and HW-SW interfaces to create developer-friendly designs.…See more Responsibilities include performance modeling, RTL design flow understanding, and trade-off analysis across quality of service, power management, security, and debug features. The position demands 4+ years of systems engineering or architecture experience with a degree in electrical engineering or computer science.

Design and architect network-on-chip (NoC) interconnect components for Qualcomm SoCs, from specification through RTL delivery. Perform micro-architecture analysis, power and performance tradeoffs, and protocol compliance evaluation for bus interconnects.…See more Deliver RTL, support verification and silicon validation teams, and collaborate with software teams on interconnect deployment. Requires strong knowledge of bus protocols (AHB, AXI, CHI), ASIC design flows, VLSI fundamentals, and experience deploying IPs in large SoC projects.

Design, implement, and optimize video processing and computer vision algorithms for mobile and embedded platforms at scale, from concept through production deployment. Profile and optimize algorithm performance across memory, compute, power, and bandwidth constraints on SoCs with embedded accelerators.…See more Lead system and algorithm-level architecture, collaborate with cross-functional hardware and software teams, and provide technical mentorship to engineers across experience levels.

As an Always On Power Management Firmware Engineer at Qualcomm, you will develop embedded firmware for managing power distribution and thermal budgets in SoC Always-On subsystems. Working with hardware and firmware teams, you will design and implement power management solutions, characterize IPs, and engage with third parties on platform enablement.…See more The role requires 4+ years of ASIC design/verification experience and proficiency with scripting, programming languages, and design verification methods. You will collaborate with cross-functional teams including hardware architects, software teams, and senior leadership to define implementation strategies and optimize for performance, power efficiency, and quality.