logic-design jobs in San Diego

Senior ASIC engineer responsible for defining, modeling, designing (digital and/or analog), optimizing, verifying, validating, implementing, and documenting IP blocks and SoCs for high-performance, low-power products. Design and architecture duties span RTL-to-GDS flow, circuit specifications, logic design, system simulation, timing, power analysis, and design verification.…See more Requires 2+ years of ASIC design/verification experience (or equivalent with advanced degree) and proficiency with EDA tools, scripting, and design verification methodologies. Works independently with cross-functional collaboration and produces detailed technical documentation.

As an ASIC RTL Design Engineer, you will define, model, design, optimize, verify, and validate IP blocks and SoCs for high-performance, low-power products. You will assist in creating architectures, circuit specifications, and logic designs based on system-level requirements, and collaborate with cross-functional teams to develop implementation strategies.…See more The role involves using EDA tools and RTL-to-GDS flows to execute design and supporting the evaluation of process flow from synthesis through place-and-route. You will work under supervision on tasks requiring multiple steps, planning, and problem-solving to deliver technical documentation for ASIC projects.

SoC Design and Integration Engineer at Qualcomm responsible for RTL design, architecture, and integration of high-performance ASICs for data center and AI applications. The role involves hands-on design and verification of complex chips, system simulation, large-scale design integration, and collaboration with cross-functional teams.…See more Candidates should have proven ASIC/FPGA design experience, knowledge of server/data center protocols, and expertise in arithmetic or machine-learning IP design. The position also values scripting, process automation, and the ability to identify flow improvements and provide silicon learnings feedback.

Qualcomm's Global CAD team is seeking an EDA/CAD software engineer to develop critical emulation tools and algorithms for VLSI design, including synthesis, partitioning, place-and-route, and clock optimization. The role requires C++ software development expertise, hands-on Linux experience, and knowledge of CAD tool development, RTL synthesis, and VLSI design concepts.…See more The engineer will work with industry-standard tools and technologies, optimize compute and storage infrastructure, and mentor team members. A Bachelor's degree in Science or Engineering is required, with preferred experience in ASIC/FPGA design, data structures, algorithms, and software design patterns.

As an ASIC Digital Design Engineer, you will define, model, design, optimize, verify, and validate IP blocks and SoCs for high-performance, low-power memory subsystems (HBM, LPDDR). You'll work with cross-functional teams to develop architectures, circuit specifications, and logic designs based on system requirements, using EDA tools to execute the RTL-to-GDS flow and custom circuit design workflows.…See more Responsibilities include creating system simulations, evaluating implementation strategies, and documenting technical specifications for ASIC projects.

Design RTL for high-performance Hexagon/NPU processor cores used in mobile SoCs, servers, IoT, and automotive applications. Work across the full ASIC design flow from RTL through GDS2, collaborating with architecture, physical design, and verification teams on timing closure, power optimization, and area reduction.…See more Develop SystemVerilog RTL, run frontend design tools (linting, CDC, LEC, CLP), and support hardware integration and design verification. Requires 2+ years of practical RTL development experience with microprocessor design knowledge.

Develop critical CAD tools and algorithms for Qualcomm's emulation infrastructure, focusing on synthesis, partitioning, place-and-route, and clock optimization for SoC designs. Optimize compute and storage, mentor team members, and apply software design principles in a Linux environment using industry-standard EDA flows.…See more Requires 2+ years of C++ development, CAD tool development, or ASIC/FPGA design experience, with hands-on knowledge of RTL synthesis, VLSI concepts, and data structures/algorithms.

As a Camera Firmware Engineer at Qualcomm, you will define, model, design, optimize, verify, validate, implement, and document IP blocks and SoCs for high-performance camera systems. You will assist in creating architectures, circuit specifications, logic designs, and system simulations based on system-level requirements, collaborating with cross-functional teams.…See more The role requires hands-on use of ASIC design tools (RTL to GDS flow, Virtuoso) and evaluation of the design flow from high-level design through synthesis, place and route, timing, and power analysis. You will write technical documentation and support the development of implementation strategies that meet system and customer requirements.

As a NoC Interconnect Design Engineer and Architect at Qualcomm, you will define, model, design, optimize, and verify network-on-chip IP blocks and SoCs for high-performance, low-power products. You will create architectures and circuit specifications based on system requirements, support the RTL-to-GDS implementation flow, and collaborate with cross-functional teams to meet customer needs.…See more The role requires hands-on use of EDA tools (RTL synthesis, place-and-route, timing/power analysis, and custom design tools like Virtuoso) and technical documentation. You will work under supervision on digital and/or analog design tasks that span from high-level specification through physical implementation.

Design and verify Digital Signal Processor (DSP) architectures for Qualcomm's mobile, machine learning, automotive, and IoT products. Develop small to complex hardware blocks independently, applying high-performance microprocessor design concepts including multi-core, multi-threaded, and low-power optimization.…See more Conduct design verification, performance analysis, and architecture tradeoff evaluation using simulators, emulators, and synthesis tools. Collaborate with cross-functional teams to ensure designs meet specifications for performance, power, and timing while staying current with industry trends in machine learning and modem technologies.