cache-coherency jobs in San Diego

Qualcomm seeks a CPU Software Architecture Sr. Staff Engineer to design and develop low-level firmware for CPU bootstrapping, power management, and debug capabilities in Snapdragon chipsets.…See more The role involves defining CPU software architecture roadmaps across Arm and RISC-V ISAs, analyzing CPU microarchitecture trade-offs (prefetching, speculation, memory ordering), and coordinating with internal teams and external partners like Arm, Google, and Microsoft. The candidate will demonstrate deep expertise in computer architecture domains such as memory consistency, coherency, virtualization, and security, with 15+ years of embedded systems experience and strong C/C++ proficiency.

Senior Staff SoC Systems Performance Engineer responsible for analyzing and defining next-generation system-on-chip architectures across mobile, automotive, and compute products. The role involves conducting performance, power, and thermal analysis; deploying simulators and profilers to identify bottlenecks; and collaborating with hardware, software, and product teams to drive architectural decisions.…See more Requires 5+ years of systems engineering experience with deep knowledge of computer architecture (CPUs, GPUs, DSPs, memory hierarchies, cache coherency) and hands-on proficiency with performance modeling tools, SystemC simulators, and profiling methodologies.

Lead Arm's SoC interconnect technology team as a senior architect with 15+ years of experience designing large-scale SoCs. Own performance modeling, microarchitecture, RTL design, and verification strategy for interconnect IP; drive adoption of industry standards (AMBA AXI/ACE/CHI, etc.) across CPU, GPU, NPU, and memory subsystems.…See more Mentor a team of architects and engineers while leading complex projects to tape-out, with expertise in coherent protocols, cache coherency, latency/bandwidth/power optimization, and system-level debug.

As a CPU SoC Verification Engineer, you will drive ARM-based SoC verification from RTL simulation through post-silicon debug, ensuring functional integrity of CPU subsystems. You'll develop robust verification environments, execute Gate Level Simulation (GLS) and timing-annotated simulations, and lead debug efforts to diagnose hardware failures and stabilize high-speed patterns in production.…See more The role requires expertise in RTL verification, cache coherency, Network-on-Chip interconnects, and high-speed bus protocols, with experience translating simulation sequences into ATE-ready formats using industry-standard EDA tools.