SOC Infrastructure IP System HW Architect
San DiegoLast seen today
Summary
Define and architect next-generation SoC infrastructure hardware components including interconnect (NoC), system cache, memory controllers, and system MMU for Qualcomm SoCs. The role requires deep expertise in multi-die/chiplet architectures, industry-standard protocols (PCIe, CXL, USB, UFS, MIPI, UCIe), and HW-SW interfaces to create developer-friendly designs. Responsibilities include performance modeling, RTL design flow understanding, and trade-off analysis across quality of service, power management, security, and debug features. The position demands 4+ years of systems engineering or architecture experience with a degree in electrical engineering or computer science.
DevOps / InfrastructureEmbedded SystemsReactArm Advanced TechnologyArm ArchitectureArm SecurityChip To Chip LinksChiplet ArchitectureCxlDebug ArchitectureDie To Die LinksFirmwareFunctional SafetyHw Sw InterfacesInterrupt HandlerMachine LearningMemory ControllerMemory TaggingMipiMpamMulti Die ArchitectureNocPciePerformance ModelingPower ManagementQuality Of ServiceRasRisc VRtl DesignSecurity ArchitectureSmmuSystem CacheUcieUfsUsbX86