hbm jobs in San Diego

Lead system-level validation strategy, planning, and content development for next-generation premium mobile and AI accelerator SoCs across emulation and silicon phases. Own end-to-end validation roadmaps, test coverage plans, and cross-domain content execution while partnering with architecture, design, firmware, and software teams.…See more Manage geographically distributed engineering teams, drive root-cause analysis on critical silicon and software issues, and champion AI/GenAI-driven validation methodologies. Requires 8+ years in SoC validation, strong understanding of modern SoC architectures (CPUs, memory subsystems, interconnects, power management, security), and demonstrated technical leadership.

Senior ASIC design engineer role focused on next-generation high-speed HBM, LPDDR, and DDR memory subsystem architecture and RTL implementation for Qualcomm products. Responsibilities include developing memory controller and NoC-based subsystem specifications, RTL coding, micro-architecture design, synthesis, timing closure, physical design support, and gate-level simulation.…See more The role requires 5+ years of ASIC/RTL design experience, 3+ years of hardware architecture experience, and expertise in high-speed digital design (1GHz+) interfacing with CPU, GPU, DSP, and multimedia processors.

As an ASIC Digital Design Engineer, you will define, model, design, optimize, verify, and validate IP blocks and SoCs for high-performance, low-power memory subsystems (HBM, LPDDR). You'll work with cross-functional teams to develop architectures, circuit specifications, and logic designs based on system requirements, using EDA tools to execute the RTL-to-GDS flow and custom circuit design workflows.…See more Responsibilities include creating system simulations, evaluating implementation strategies, and documenting technical specifications for ASIC projects.

Senior Staff Center of Excellence Emulation Engineer responsible for executing emulation test plans, developing and optimizing complex SoC and subsystem hardware models across Synopsys, Cadence, and Siemens platforms. The role involves collaborating with RTL design, verification, and firmware teams to debug cross-layer issues, automate emulation flows through scripting, and drive performance optimization.…See more Requires 5–7 years of emulation experience (or 3–5 with advanced degree), expertise in SystemVerilog/UVM, and strong knowledge of processor architecture, I/O protocols, and memory technologies.