NoC Interconnect Design Engineer and Architect

$115,600 – $173,400 · Posted 1 day ago

San DiegoLast seen today

Summary

Design and architect network-on-chip (NoC) interconnect components for Qualcomm SoCs, from specification through RTL delivery. Perform micro-architecture analysis, power and performance tradeoffs, and protocol compliance evaluation for bus interconnects. Deliver RTL, support verification and silicon validation teams, and collaborate with software teams on interconnect deployment. Requires strong knowledge of bus protocols (AHB, AXI, CHI), ASIC design flows, VLSI fundamentals, and experience deploying IPs in large SoC projects.

Design Systems Embedded Systems React Ahb Asic Design Asic Flow Axi Bus Protocols Chi Cpu Architecture Fpga Lint Micro Architecture Noc Network On Chip Performance Analysis Post Silicon Debug Power Analysis Power Tools Rtl Design Sta Static Timing Analysis Synthesis Vlsi