Staff Engineer

Expired

Info Way Solutions

Posted 29 days ago

San DiegoLast seen 27 days ago

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Summary

Staff Engineer role focused on CPU design, RTL development, and physical design for next-generation high-performance, low-power SoCs. Responsibilities span microarchitecture definition, Verilog/SystemVerilog RTL coding, synthesis, physical implementation (floorplanning, placement, routing, timing closure), and PPA optimization. Will collaborate across architecture, verification, DFT, and post-silicon teams, and develop automation scripts in Python, Tcl, Perl, or Shell. Requires 4–10 years in ASIC/SoC, CPU, RTL, or physical design, strong digital design fundamentals, and hands-on experience with CPU microarchitecture and design closure flows.

Embedded Systems Software Development Python Asic Branch Prediction Cache Cadence Innovus Cdc Clock Tree Synthesis Cpu Microarchitecture Crosstalk Dft Eco Electromigration Floorplanning Formal Verification Ir Drop Lint Linux Low Power Design Memory Hierarchy Mmmc Mmu Out Of Order Execution Perl Physical Design Physical Verification Placement Ppa Optimization Primetime Routing Rtl Design Shell Signal Integrity Soc Sta Static Timing Analysis Synopsys Fusion Compiler Synthesis Systemverilog Tcl Timing Closure Unix Upf Verilog