asic-design jobs in San Diego

Senior ASIC engineer responsible for defining, modeling, designing (digital and/or analog), optimizing, verifying, validating, implementing, and documenting IP blocks and SoCs for high-performance, low-power products. Design and architecture duties span RTL-to-GDS flow, circuit specifications, logic design, system simulation, timing, power analysis, and design verification.…See more Requires 2+ years of ASIC design/verification experience (or equivalent with advanced degree) and proficiency with EDA tools, scripting, and design verification methodologies. Works independently with cross-functional collaboration and produces detailed technical documentation.

As an ASIC RTL Design Engineer, you will define, model, design, optimize, verify, and validate IP blocks and SoCs for high-performance, low-power products. You will assist in creating architectures, circuit specifications, and logic designs based on system-level requirements, and collaborate with cross-functional teams to develop implementation strategies.…See more The role involves using EDA tools and RTL-to-GDS flows to execute design and supporting the evaluation of process flow from synthesis through place-and-route. You will work under supervision on tasks requiring multiple steps, planning, and problem-solving to deliver technical documentation for ASIC projects.

The SOC Platform Architect will work with hardware designers to gather and analyze power estimation data for Qualcomm SoC infrastructure IPs (interconnect, system cache, memory controllers, MMU), identify architectural bottlenecks and bugs, and propose optimizations. The role requires deep ASIC design and computer architecture expertise, along with understanding of system-level design, hardware-software trade-offs, and complete silicon design flows.…See more The candidate will coordinate with domain leads to ensure robust infrastructure deployment aligned with product requirements. Required background: 7+ years ASIC design/verification (or 5+ with a master's degree).

Senior ASIC design engineer role focused on next-generation high-speed HBM, LPDDR, and DDR memory subsystem architecture and RTL implementation for Qualcomm products. Responsibilities include developing memory controller and NoC-based subsystem specifications, RTL coding, micro-architecture design, synthesis, timing closure, physical design support, and gate-level simulation.…See more The role requires 5+ years of ASIC/RTL design experience, 3+ years of hardware architecture experience, and expertise in high-speed digital design (1GHz+) interfacing with CPU, GPU, DSP, and multimedia processors.

SoC Design and Integration Engineer at Qualcomm responsible for RTL design, architecture, and integration of high-performance ASICs for data center and AI applications. The role involves hands-on design and verification of complex chips, system simulation, large-scale design integration, and collaboration with cross-functional teams.…See more Candidates should have proven ASIC/FPGA design experience, knowledge of server/data center protocols, and expertise in arithmetic or machine-learning IP design. The position also values scripting, process automation, and the ability to identify flow improvements and provide silicon learnings feedback.

Qualcomm's Global CAD team is seeking an EDA/CAD software engineer to develop critical emulation tools and algorithms for VLSI design, including synthesis, partitioning, place-and-route, and clock optimization. The role requires C++ software development expertise, hands-on Linux experience, and knowledge of CAD tool development, RTL synthesis, and VLSI design concepts.…See more The engineer will work with industry-standard tools and technologies, optimize compute and storage infrastructure, and mentor team members. A Bachelor's degree in Science or Engineering is required, with preferred experience in ASIC/FPGA design, data structures, algorithms, and software design patterns.

Develop critical CAD tools and algorithms for Qualcomm's emulation infrastructure, focusing on VLSI design automation including synthesis, partitioning, place-and-route, and clock optimization. Work with industry-standard EDA technologies and C++ to build software that addresses SoC-specific needs, optimize compute and storage, and mentor team members.…See more Requires 2+ years of C++ development, CAD tool experience, and hands-on Linux proficiency, with strong knowledge of RTL synthesis, logic design, and software design principles.

Design and develop uniform global methodologies for emulation build generation and debug across FPGA-based emulation platforms at Qualcomm's SoC digital hardware organization. Collaborate with architects, designers, verification engineers, and software teams to support pre-silicon prototyping and bring-up of new SoC designs.…See more Debug low-level software and hardware issues using tools like JTAG and kernel debuggers, with expertise in Verilog/SystemVerilog, FPGA platforms (Xilinx/Intel), and scripting languages. Requires 4+ years of ASIC design, verification, validation, or integration experience, with preferred 5+ years in emulation and silicon environments.

As an ASIC Digital Design Engineer, you will define, model, design, optimize, verify, and validate IP blocks and SoCs for high-performance, low-power memory subsystems (HBM, LPDDR). You'll work with cross-functional teams to develop architectures, circuit specifications, and logic designs based on system requirements, using EDA tools to execute the RTL-to-GDS flow and custom circuit design workflows.…See more Responsibilities include creating system simulations, evaluating implementation strategies, and documenting technical specifications for ASIC projects.

Design and optimize Network-on-Chip (NoC) architectures for high-performance Qualcomm SoCs with focus on physical implementation and PPA (power, performance, area) goals. Responsibilities include floorplan-driven architecture design, physical-aware synthesis strategies, clock tree planning, power analysis, timing closure, and custom placement/routing techniques.…See more Requires deep expertise in ASIC physical design, NoC protocols (AMBA, cache coherency), and scripting in Python, Perl, TCL, and C to analyze and optimize latency, area, performance, and power metrics.

Design RTL for high-performance Hexagon/NPU processor cores used in mobile SoCs, servers, IoT, and automotive applications. Work across the full ASIC design flow from RTL through GDS2, collaborating with architecture, physical design, and verification teams on timing closure, power optimization, and area reduction.…See more Develop SystemVerilog RTL, run frontend design tools (linting, CDC, LEC, CLP), and support hardware integration and design verification. Requires 2+ years of practical RTL development experience with microprocessor design knowledge.

Design and develop secure provisioning and test software for Amazon's custom silicon, focusing on OTP/eFuse programming, cryptographic key injection, and debug-access flows. Own the full lifecycle from ATE integration with HSMs and key-management systems through post-provisioned device validation, ensuring secure boot and device identity provisioning at scale.…See more Build reusable ATE libraries, test utilities, and automation frameworks using Python and/or C/C++, applying strong software engineering practices and collaborating with ASIC design, DFT, and security teams. Lead technical and security reviews, identify gaps throughout the product lifecycle, and drive best practices across the team.

Develop critical CAD tools and algorithms for VLSI emulation infrastructure at Qualcomm, focusing on synthesis, partitioning, place-and-route, and clock optimization. The role involves C++ software development, Linux-based systems, and hands-on CAD tool design while mentoring team members.…See more Candidates should have 2+ years of ASIC/FPGA design or CAD tool development experience, with strong foundations in data structures, algorithms, and RTL synthesis concepts.

Develop critical CAD tools and algorithms for Qualcomm's emulation infrastructure, focusing on synthesis, partitioning, place-and-route, and clock optimization for SoC designs. Optimize compute and storage, mentor team members, and apply software design principles in a Linux environment using industry-standard EDA flows.…See more Requires 2+ years of C++ development, CAD tool development, or ASIC/FPGA design experience, with hands-on knowledge of RTL synthesis, VLSI concepts, and data structures/algorithms.

As a Camera Firmware Engineer at Qualcomm, you will define, model, design, optimize, verify, validate, implement, and document IP blocks and SoCs for high-performance camera systems. You will assist in creating architectures, circuit specifications, logic designs, and system simulations based on system-level requirements, collaborating with cross-functional teams.…See more The role requires hands-on use of ASIC design tools (RTL to GDS flow, Virtuoso) and evaluation of the design flow from high-level design through synthesis, place and route, timing, and power analysis. You will write technical documentation and support the development of implementation strategies that meet system and customer requirements.

As an Applications Engineering Consultant for Siemens EDA's Emulation division, you will provide technical sales support and hands-on expertise to customers evaluating and deploying Siemens Veloce Strato emulation and prototyping solutions. You'll work directly with customers during product evaluations, troubleshoot technical obstacles, deliver presentations on product features, and communicate customer requirements back to product development teams.…See more The role requires 7+ years in chip/ASIC design, verification, or emulation/prototyping, with deep expertise in SystemVerilog/Verilog/VHDL, RTL design, industry emulation tools (Veloce, Palladium, ZeBu), and simulation environments (Questa, VCS, Incisive). You'll leverage scripting languages (Python, Perl, Tcl, shell) and EDA tool integration knowledge to help customers optimize their design flows and build long-term technical relationships.

As a NoC Interconnect Design Engineer and Architect at Qualcomm, you will define, model, design, optimize, and verify network-on-chip IP blocks and SoCs for high-performance, low-power products. You will create architectures and circuit specifications based on system requirements, support the RTL-to-GDS implementation flow, and collaborate with cross-functional teams to meet customer needs.…See more The role requires hands-on use of EDA tools (RTL synthesis, place-and-route, timing/power analysis, and custom design tools like Virtuoso) and technical documentation. You will work under supervision on digital and/or analog design tasks that span from high-level specification through physical implementation.

As a SOC Platform Architect at Qualcomm's ASIC Engineering group, you will define and architect platform infrastructure hardware IP components (NOC, System Cache, Memory Controllers, System MMU) for next-generation SoCs. You'll work with hardware architects to gather requirements, develop deployment specifications, and coordinate with domain leads to create robust infrastructure deployment plans based on product needs.…See more The role requires strong ASIC design and computer architecture expertise, system-level design understanding, and knowledge of HW-SW feature trade-offs across the complete silicon design flow.

As Server SoC Security Architect at Qualcomm, you will define system-level security architecture for Snapdragon processors across data center, automotive, and mobile platforms. You'll establish hardware and software security requirements, specify and review SoC-level security mechanisms, conduct threat analysis, and serve as technical liaison to product management and standards teams.…See more The role requires 10+ years in SoC security (architecture and design), 5+ years in compute/data center SoC architecture, and deep expertise in confidential compute (RME, TDX, SEV-SNP, RISC-V CoVE), root of trust, TEE, and secure boot. You'll work cross-functionally with hardware/software engineering, services, and OEM partners to deliver industry-leading security solutions.

Design and architect network-on-chip (NoC) interconnect components for Qualcomm SoCs, from specification through RTL delivery. Perform micro-architecture analysis, power and performance tradeoffs, and protocol compliance evaluation for bus interconnects.…See more Deliver RTL, support verification and silicon validation teams, and collaborate with software teams on interconnect deployment. Requires strong knowledge of bus protocols (AHB, AXI, CHI), ASIC design flows, VLSI fundamentals, and experience deploying IPs in large SoC projects.

Develop critical CAD tools and algorithms for VLSI emulation at Qualcomm, focusing on RTL synthesis, clock tree optimization, place-and-route, and partitioning for complex SoCs. Write C++ software leveraging industry-standard CAD technologies and Linux infrastructure, with responsibilities ranging from algorithm design to mentoring team members.…See more This role requires strong software engineering fundamentals (data structures, design patterns, algorithms) combined with hands-on ASIC/FPGA and CAD tool development experience.

As an Always On Power Management Firmware Engineer at Qualcomm, you will develop embedded firmware for managing power distribution and thermal budgets in SoC Always-On subsystems. Working with hardware and firmware teams, you will design and implement power management solutions, characterize IPs, and engage with third parties on platform enablement.…See more The role requires 4+ years of ASIC design/verification experience and proficiency with scripting, programming languages, and design verification methods. You will collaborate with cross-functional teams including hardware architects, software teams, and senior leadership to define implementation strategies and optimize for performance, power efficiency, and quality.