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eda-tools jobs in San Diego

$101,400 – $152,200 · Posted 1 day ago

As a NoC Interconnect Design Engineer and Architect, you will define, model, design, optimize, verify, validate, implement, and document IP block and SoC development for high-performance, low-power products. You will create architectures, circuit specifications, logic designs, and system simulations based on system-level requirements, and collaborate with cross-functional teams to develop implementation strategies.… The role requires hands-on use of design tools and EDA flows (RTL to GDS, Virtuoso) to execute the architecture and design of specific IC components, along with technical documentation for ASIC projects.

San DiegoLast seen today
$121,800 – $182,600 · Posted 10 days ago

Senior ASIC engineer responsible for defining, modeling, designing (digital and/or analog), optimizing, verifying, validating, implementing, and documenting IP blocks and SoCs for high-performance, low-power products. Design and architecture duties span RTL-to-GDS flow, circuit specifications, logic design, system simulation, timing, power analysis, and design verification.… Requires 2+ years of ASIC design/verification experience (or equivalent with advanced degree) and proficiency with EDA tools, scripting, and design verification methodologies. Works independently with cross-functional collaboration and produces detailed technical documentation.

San DiegoLast seen 8 days ago
$101,400 – $152,200 · Posted 13 days ago

As an ASIC RTL Design Engineer, you will define, model, design, optimize, verify, and validate IP blocks and SoCs for high-performance, low-power products. You will assist in creating architectures, circuit specifications, and logic designs based on system-level requirements, and collaborate with cross-functional teams to develop implementation strategies.… The role involves using EDA tools and RTL-to-GDS flows to execute design and supporting the evaluation of process flow from synthesis through place-and-route. You will work under supervision on tasks requiring multiple steps, planning, and problem-solving to deliver technical documentation for ASIC projects.

San DiegoLast seen 11 days ago
$138,000 – $197,000 · Posted 20 days ago

As a CPU SoC Verification Engineer at Google, you will drive ARM-based SoC verification from RTL simulation through post-silicon debug, ensuring functional integrity of CPU subsystems. You will develop robust verification environments, execute Gate Level Simulation (GLS) and timing-annotated workflows, and partner with ATE teams to diagnose hardware failures and stabilize production patterns.… The role requires 4+ years of ARM SoC verification experience including cache coherency, NoC interconnects, high-speed bus protocols, and PVT corner analysis. You will translate simulation sequences into production-ready formats and debug complex hardware failures in both virtual and physical silicon environments.

San DiegoLast seen 18 days ago
$101,400 – $152,200 · Posted 21 days ago

As an ASIC Digital Design Engineer, you will define, model, design, optimize, verify, and validate IP blocks and SoCs for high-performance, low-power memory subsystems (HBM, LPDDR). You'll work with cross-functional teams to develop architectures, circuit specifications, and logic designs based on system requirements, using EDA tools to execute the RTL-to-GDS flow and custom circuit design workflows.… Responsibilities include creating system simulations, evaluating implementation strategies, and documenting technical specifications for ASIC projects.

San DiegoLast seen 19 days ago
$99,400 – $149,200 · Posted 1 month ago

As a Camera Firmware Engineer at Qualcomm, you will define, model, design, optimize, verify, validate, implement, and document IP blocks and SoCs for high-performance camera systems. You will assist in creating architectures, circuit specifications, logic designs, and system simulations based on system-level requirements, collaborating with cross-functional teams.… The role requires hands-on use of ASIC design tools (RTL to GDS flow, Virtuoso) and evaluation of the design flow from high-level design through synthesis, place and route, timing, and power analysis. You will write technical documentation and support the development of implementation strategies that meet system and customer requirements.

San DiegoLast seen 15 days ago
$146,700 – $293,400 · Posted 1 month ago

As an Applications Engineering Consultant for Siemens EDA emulation tools, you will provide technical sales support to the Americas region, deploying Veloce Strato emulation and prototyping solutions for semiconductor and electronics companies. You will work directly with customers during product evaluations, troubleshoot technical obstacles, deliver presentations on new features, and gather feedback to improve products.… The role requires 7+ years of chip design, verification, simulation, or emulation experience with deep expertise in SystemVerilog/Verilog/VHDL, RTL coding, ASIC debug, and familiarity with industry emulation platforms (Veloce, Palladium, ZeBu) and simulation environments (Questa, Incisive, VCS). You will also need proficiency in scripting languages, Transaction Level Modeling, and the ability to communicate complex technical solutions to customers at multiple organizational levels.

San DiegoLast seen 1 month ago
Posted 1 month ago

As an Applications Engineering Consultant for Siemens EDA's Emulation division, you will provide technical sales support and hands-on expertise to customers evaluating and deploying Siemens Veloce Strato emulation and prototyping solutions. You'll work directly with customers during product evaluations, troubleshoot technical obstacles, deliver presentations on product features, and communicate customer requirements back to product development teams.… The role requires 7+ years in chip/ASIC design, verification, or emulation/prototyping, with deep expertise in SystemVerilog/Verilog/VHDL, RTL design, industry emulation tools (Veloce, Palladium, ZeBu), and simulation environments (Questa, VCS, Incisive). You'll leverage scripting languages (Python, Perl, Tcl, shell) and EDA tool integration knowledge to help customers optimize their design flows and build long-term technical relationships.

San DiegoLast seen 1 month ago
$98,500 – $147,700 · Posted 1 month ago

As a NoC Interconnect Design Engineer and Architect at Qualcomm, you will define, model, design, optimize, and verify network-on-chip IP blocks and SoCs for high-performance, low-power products. You will create architectures and circuit specifications based on system requirements, support the RTL-to-GDS implementation flow, and collaborate with cross-functional teams to meet customer needs.… The role requires hands-on use of EDA tools (RTL synthesis, place-and-route, timing/power analysis, and custom design tools like Virtuoso) and technical documentation. You will work under supervision on digital and/or analog design tasks that span from high-level specification through physical implementation.

San DiegoLast seen 1 month ago
Posted 1 month ago

As a CPU SoC Verification Engineer, you will drive ARM-based SoC verification from RTL simulation through post-silicon debug, ensuring functional integrity of CPU subsystems. You'll develop robust verification environments, execute Gate Level Simulation (GLS) and timing-annotated simulations, and lead debug efforts to diagnose hardware failures and stabilize high-speed patterns in production.… The role requires expertise in RTL verification, cache coherency, Network-on-Chip interconnects, and high-speed bus protocols, with experience translating simulation sequences into ATE-ready formats using industry-standard EDA tools.

San DiegoLast seen 1 month ago
$230,398 – $322,557 · Posted 1 month ago

Blue Origin seeks a Technical Program Manager to lead SoC (System-on-Chip) development programs from requirements through production. The role requires managing complex hardware and semiconductor programs across multiple lifecycle phases, coordinating with highly technical engineering teams, external suppliers, and IP providers.… Responsibilities include change management, build-versus-buy decisions, supplier strategy, scheduling, risk management, and translating between detailed technical execution and business objectives. The ideal candidate has 7+ years of technical program management experience, a strong background in IC/SoC development, analog/mixed-signal design, digital ASIC, RF systems, or satellite communications, plus demonstrated ability to lead through tapeout, silicon bring-up, qualification, and production ramp.

San DiegoLast seen 29 days ago