Lead validation of clock, power, reset, and power-management architectures for next-generation AI accelerator SoCs, owning pre-silicon and post-silicon validation of clocking infrastructure, PMIC integration, DVFS, and low-power features across multi-die systems. Develop bare-metal validation frameworks, test plans, and automation using C, Python, and Perl; debug complex power, performance, and stability issues in collaboration with architecture, design, verification, and firmware teams.… Define validation methodologies and stress workloads for AI training and inference scenarios, and drive power subsystem bring-up readiness across program milestones. Requires 5+ years of SoC validation experience, proficiency in C and Python, hands-on lab instrumentation skills, and prior exposure to clock and power validation.
systemverilog jobs in San Diego
SoC Design and Integration Engineer at Qualcomm responsible for RTL design, architecture, and integration of high-performance ASICs for data center and AI applications. The role involves hands-on design and verification of complex chips, system simulation, large-scale design integration, and collaboration with cross-functional teams.… Candidates should have proven ASIC/FPGA design experience, knowledge of server/data center protocols, and expertise in arithmetic or machine-learning IP design. The position also values scripting, process automation, and the ability to identify flow improvements and provide silicon learnings feedback.
Design and develop uniform global methodologies for emulation build generation and debug across FPGA-based emulation platforms at Qualcomm's SoC digital hardware organization. Collaborate with architects, designers, verification engineers, and software teams to support pre-silicon prototyping and bring-up of new SoC designs.… Debug low-level software and hardware issues using tools like JTAG and kernel debuggers, with expertise in Verilog/SystemVerilog, FPGA platforms (Xilinx/Intel), and scripting languages. Requires 4+ years of ASIC design, verification, validation, or integration experience, with preferred 5+ years in emulation and silicon environments.
As an ASIC Digital Design Engineer, you will define, model, design, optimize, verify, and validate IP blocks and SoCs for high-performance, low-power memory subsystems (HBM, LPDDR). You'll work with cross-functional teams to develop architectures, circuit specifications, and logic designs based on system requirements, using EDA tools to execute the RTL-to-GDS flow and custom circuit design workflows.… Responsibilities include creating system simulations, evaluating implementation strategies, and documenting technical specifications for ASIC projects.
Design RTL for high-performance Hexagon/NPU processor cores used in mobile SoCs, servers, IoT, and automotive applications. Work across the full ASIC design flow from RTL through GDS2, collaborating with architecture, physical design, and verification teams on timing closure, power optimization, and area reduction.… Develop SystemVerilog RTL, run frontend design tools (linting, CDC, LEC, CLP), and support hardware integration and design verification. Requires 2+ years of practical RTL development experience with microprocessor design knowledge.
Staff Engineer
ExpiredStaff Engineer role focused on CPU design, RTL development, and physical design for next-generation high-performance, low-power SoCs. Responsibilities span microarchitecture definition, Verilog/SystemVerilog RTL coding, synthesis, physical implementation (floorplanning, placement, routing, timing closure), and PPA optimization.… Will collaborate across architecture, verification, DFT, and post-silicon teams, and develop automation scripts in Python, Tcl, Perl, or Shell. Requires 4–10 years in ASIC/SoC, CPU, RTL, or physical design, strong digital design fundamentals, and hands-on experience with CPU microarchitecture and design closure flows.
As an Applications Engineering Consultant for Siemens EDA emulation tools, you will provide technical sales support to the Americas region, deploying Veloce Strato emulation and prototyping solutions for semiconductor and electronics companies. You will work directly with customers during product evaluations, troubleshoot technical obstacles, deliver presentations on new features, and gather feedback to improve products.… The role requires 7+ years of chip design, verification, simulation, or emulation experience with deep expertise in SystemVerilog/Verilog/VHDL, RTL coding, ASIC debug, and familiarity with industry emulation platforms (Veloce, Palladium, ZeBu) and simulation environments (Questa, Incisive, VCS). You will also need proficiency in scripting languages, Transaction Level Modeling, and the ability to communicate complex technical solutions to customers at multiple organizational levels.
As an Applications Engineering Consultant for Siemens EDA's Emulation division, you will provide technical sales support and hands-on expertise to customers evaluating and deploying Siemens Veloce Strato emulation and prototyping solutions. You'll work directly with customers during product evaluations, troubleshoot technical obstacles, deliver presentations on product features, and communicate customer requirements back to product development teams.… The role requires 7+ years in chip/ASIC design, verification, or emulation/prototyping, with deep expertise in SystemVerilog/Verilog/VHDL, RTL design, industry emulation tools (Veloce, Palladium, ZeBu), and simulation environments (Questa, VCS, Incisive). You'll leverage scripting languages (Python, Perl, Tcl, shell) and EDA tool integration knowledge to help customers optimize their design flows and build long-term technical relationships.
As a Staff Product Security Engineer at Qualcomm, you will develop and deploy hardware and software security features across the product lifecycle, perform comprehensive security assessments including vulnerability analysis and threat modeling, and conduct security code reviews. You will identify and remediate security risks, respond to product security incidents, and develop training and tools to embed secure development practices.… The role requires a strong foundation in programming languages (C, C++, Java, Python, SystemVerilog) and the ability to work independently on complex security engineering challenges with influence over organizational decisions.
Senior Staff Center of Excellence Emulation Engineer responsible for executing emulation test plans, developing and optimizing complex SoC and subsystem hardware models across Synopsys, Cadence, and Siemens platforms. The role involves collaborating with RTL design, verification, and firmware teams to debug cross-layer issues, automate emulation flows through scripting, and drive performance optimization.… Requires 5–7 years of emulation experience (or 3–5 with advanced degree), expertise in SystemVerilog/UVM, and strong knowledge of processor architecture, I/O protocols, and memory technologies.
Senior Embedded Firmware Design Engineer at Semtech responsible for defining, developing, and optimizing embedded firmware for low-power mixed-signal circuits from specification through production support. Role includes designing hardware-firmware architectures, implementing ML-based inference firmware, conducting pre- and post-silicon validation, and mentoring junior engineers.… Requires 8–10 years of embedded firmware experience for mixed-signal ICs, strong C/C++ and assembly proficiency, deep knowledge of MCU architectures (ARM, RISC-V, STM32), and expertise in real-time systems, signal processing, and design-for-test methodologies.
As an Always On Power Management Firmware Engineer at Qualcomm, you will develop embedded firmware for managing power distribution and thermal budgets in SoC Always-On subsystems. Working with hardware and firmware teams, you will design and implement power management solutions, characterize IPs, and engage with third parties on platform enablement.… The role requires 4+ years of ASIC design/verification experience and proficiency with scripting, programming languages, and design verification methods. You will collaborate with cross-functional teams including hardware architects, software teams, and senior leadership to define implementation strategies and optimize for performance, power efficiency, and quality.