Sr. Formal Verification Engineer, Amazon Leo

Posted 1 day ago

San DiegoLast seen today

Summary

Senior Formal Verification Engineer role focused on championing formal verification strategies for Amazon's custom silicon (SoC/NoC designs). The engineer will develop reusable formal verification infrastructure, drive proof convergence on complex designs, mentor DV engineers in SVA and formal techniques, and integrate formal methods into CI/CD pipelines. Requires 8+ years of ASIC/SoC verification experience with deep expertise in JasperGold/Questa Formal, SystemVerilog Assertions, and formal applications (FPV, equivalence checking, connectivity/register verification); proficiency with AI/LLM tools to accelerate formal workflows is expected.

Quality Assurance Software Development Python AI Asic Verification CI CD Connectivity Checking Coverage Analysis Dsp Architecture Emulation Verification Equivalence Checking Formal Verification Fpv Formal Property Verification Jaspergold LLM Large Language Models Modem Architecture Noc Verification Perl Phy Architecture Proof Convergence Questa Formal Register Verification Satellite Communications Soc Verification Systemverilog Systemverilog Assertions Sva Tcl Uvm