Principal Modem PHY IP Design Verification Engineer - Terawave

Summary

Principal-level verification engineer for modem PHY IP design at Blue Origin's Terawave division. Requires 10+ years of ASIC/SoC verification experience, particularly in modem/baseband verification using SystemVerilog and UVM. Responsibilities include developing constrained-random and directed test strategies, correlating RTL behavior against reference models, defining coverage metrics, debugging design issues, supporting FPGA/emulation/post-silicon validation, and collaborating with PHY algorithm, architecture, and RTL teams. Expertise in modem PHY areas (OFDM, synchronization, channel estimation, FEC, MIMO/beamforming, fixed-point signal processing) and scripting automation required.