Lead validation of clock, power, reset, and power-management architectures for next-generation AI accelerator SoCs, owning pre-silicon and post-silicon validation of clocking infrastructure, PMIC integration, DVFS, and low-power features across multi-die systems. Develop bare-metal validation frameworks, test plans, and automation using C, Python, and Perl; debug complex power, performance, and stability issues in collaboration with architecture, design, verification, and firmware teams.… Define validation methodologies and stress workloads for AI training and inference scenarios, and drive power subsystem bring-up readiness across program milestones. Requires 5+ years of SoC validation experience, proficiency in C and Python, hands-on lab instrumentation skills, and prior exposure to clock and power validation.