synthesis jobs in San Diego

Lead ASIC implementation for Amazon Leo's satellite communication chips, owning the digital SOC design flow from RTL through physical design sign-off. Develop chip power intent using UPF, set up synthesis and place-and-route flows for deep sub-micron nodes, validate timing and design closure, and coordinate with RFIC and P&R teams to ensure production-ready tapeouts.…See more Requires 8+ years of ASIC implementation experience including synthesis, STA, and multi-power-domain design on 16nm or smaller technology nodes.

Implementation engineer for Amazon Leo's satellite communications chip design, responsible for defining and implementing digital SOCs for Low Earth Orbit satellite modems and gateways. The role involves developing chip power intent using UPF, setting up logic and physical synthesis flows across technology nodes, validating designs at RTL and netlist levels, performing timing and power analysis, and leading sign-off.…See more Requires 5+ years of ASIC implementation experience including synthesis, static timing analysis, place-and-route for deep sub-micron nodes (16nm or smaller), and a proven track record of high-volume production tape-outs.

Senior ASIC engineer responsible for defining, modeling, designing (digital and/or analog), optimizing, verifying, validating, implementing, and documenting IP blocks and SoCs for high-performance, low-power products. Design and architecture duties span RTL-to-GDS flow, circuit specifications, logic design, system simulation, timing, power analysis, and design verification.…See more Requires 2+ years of ASIC design/verification experience (or equivalent with advanced degree) and proficiency with EDA tools, scripting, and design verification methodologies. Works independently with cross-functional collaboration and produces detailed technical documentation.

As an ASIC RTL Design Engineer, you will define, model, design, optimize, verify, and validate IP blocks and SoCs for high-performance, low-power products. You will assist in creating architectures, circuit specifications, and logic designs based on system-level requirements, and collaborate with cross-functional teams to develop implementation strategies.…See more The role involves using EDA tools and RTL-to-GDS flows to execute design and supporting the evaluation of process flow from synthesis through place-and-route. You will work under supervision on tasks requiring multiple steps, planning, and problem-solving to deliver technical documentation for ASIC projects.

Senior ASIC design engineer role focused on next-generation high-speed HBM, LPDDR, and DDR memory subsystem architecture and RTL implementation for Qualcomm products. Responsibilities include developing memory controller and NoC-based subsystem specifications, RTL coding, micro-architecture design, synthesis, timing closure, physical design support, and gate-level simulation.…See more The role requires 5+ years of ASIC/RTL design experience, 3+ years of hardware architecture experience, and expertise in high-speed digital design (1GHz+) interfacing with CPU, GPU, DSP, and multimedia processors.

Design and develop uniform global methodologies for emulation build generation and debug across FPGA-based emulation platforms at Qualcomm's SoC digital hardware organization. Collaborate with architects, designers, verification engineers, and software teams to support pre-silicon prototyping and bring-up of new SoC designs.…See more Debug low-level software and hardware issues using tools like JTAG and kernel debuggers, with expertise in Verilog/SystemVerilog, FPGA platforms (Xilinx/Intel), and scripting languages. Requires 4+ years of ASIC design, verification, validation, or integration experience, with preferred 5+ years in emulation and silicon environments.

As an ASIC Digital Design Engineer, you will define, model, design, optimize, verify, and validate IP blocks and SoCs for high-performance, low-power memory subsystems (HBM, LPDDR). You'll work with cross-functional teams to develop architectures, circuit specifications, and logic designs based on system requirements, using EDA tools to execute the RTL-to-GDS flow and custom circuit design workflows.…See more Responsibilities include creating system simulations, evaluating implementation strategies, and documenting technical specifications for ASIC projects.

Design RTL for high-performance Hexagon/NPU processor cores used in mobile SoCs, servers, IoT, and automotive applications. Work across the full ASIC design flow from RTL through GDS2, collaborating with architecture, physical design, and verification teams on timing closure, power optimization, and area reduction.…See more Develop SystemVerilog RTL, run frontend design tools (linting, CDC, LEC, CLP), and support hardware integration and design verification. Requires 2+ years of practical RTL development experience with microprocessor design knowledge.

As a Camera Firmware Engineer at Qualcomm, you will define, model, design, optimize, verify, validate, implement, and document IP blocks and SoCs for high-performance camera systems. You will assist in creating architectures, circuit specifications, logic designs, and system simulations based on system-level requirements, collaborating with cross-functional teams.…See more The role requires hands-on use of ASIC design tools (RTL to GDS flow, Virtuoso) and evaluation of the design flow from high-level design through synthesis, place and route, timing, and power analysis. You will write technical documentation and support the development of implementation strategies that meet system and customer requirements.

Staff Engineer role focused on CPU design, RTL development, and physical design for next-generation high-performance, low-power SoCs. Responsibilities span microarchitecture definition, Verilog/SystemVerilog RTL coding, synthesis, physical implementation (floorplanning, placement, routing, timing closure), and PPA optimization.…See more Will collaborate across architecture, verification, DFT, and post-silicon teams, and develop automation scripts in Python, Tcl, Perl, or Shell. Requires 4–10 years in ASIC/SoC, CPU, RTL, or physical design, strong digital design fundamentals, and hands-on experience with CPU microarchitecture and design closure flows.

As a NoC Interconnect Design Engineer and Architect at Qualcomm, you will define, model, design, optimize, and verify network-on-chip IP blocks and SoCs for high-performance, low-power products. You will create architectures and circuit specifications based on system requirements, support the RTL-to-GDS implementation flow, and collaborate with cross-functional teams to meet customer needs.…See more The role requires hands-on use of EDA tools (RTL synthesis, place-and-route, timing/power analysis, and custom design tools like Virtuoso) and technical documentation. You will work under supervision on digital and/or analog design tasks that span from high-level specification through physical implementation.

Design and architect network-on-chip (NoC) interconnect components for Qualcomm SoCs, from specification through RTL delivery. Perform micro-architecture analysis, power and performance tradeoffs, and protocol compliance evaluation for bus interconnects.…See more Deliver RTL, support verification and silicon validation teams, and collaborate with software teams on interconnect deployment. Requires strong knowledge of bus protocols (AHB, AXI, CHI), ASIC design flows, VLSI fundamentals, and experience deploying IPs in large SoC projects.

Blue Origin seeks a Technical Program Manager to lead SoC (System-on-Chip) development programs from requirements through production. The role requires managing complex hardware and semiconductor programs across multiple lifecycle phases, coordinating with highly technical engineering teams, external suppliers, and IP providers.…See more Responsibilities include change management, build-versus-buy decisions, supplier strategy, scheduling, risk management, and translating between detailed technical execution and business objectives. The ideal candidate has 7+ years of technical program management experience, a strong background in IC/SoC development, analog/mixed-signal design, digital ASIC, RF systems, or satellite communications, plus demonstrated ability to lead through tapeout, silicon bring-up, qualification, and production ramp.