Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer

$145,600 – $218,400 · Posted 6 days ago

San DiegoLast seen 4 days ago

Summary

Senior ASIC design engineer role focused on next-generation high-speed HBM, LPDDR, and DDR memory subsystem architecture and RTL implementation for Qualcomm products. Responsibilities include developing memory controller and NoC-based subsystem specifications, RTL coding, micro-architecture design, synthesis, timing closure, physical design support, and gate-level simulation. The role requires 5+ years of ASIC/RTL design experience, 3+ years of hardware architecture experience, and expertise in high-speed digital design (1GHz+) interfacing with CPU, GPU, DSP, and multimedia processors.

Design Systems Embedded Systems Arm Architecture Asic Design Cache Controller Design Cpu Architecture Ddr Front End Design Gate Level Simulation Hardware Architecture Hbm High Speed Digital Design Isa Specification L3 Cache Lpddr Memory Controller Design Memory Transaction Ordering Noc Architecture Physical Design Power Analysis Rtl Coding Rtl Verification Sram Design Synthesis Timing Closure Verilog Vhdl X86 Architecture