timing-analysis jobs in San Diego

As a NoC Interconnect Design Engineer and Architect, you will define, model, design, optimize, verify, validate, implement, and document IP block and SoC development for high-performance, low-power products. You will create architectures, circuit specifications, logic designs, and system simulations based on system-level requirements, and collaborate with cross-functional teams to develop implementation strategies.…See more The role requires hands-on use of design tools and EDA flows (RTL to GDS, Virtuoso) to execute the architecture and design of specific IC components, along with technical documentation for ASIC projects.

Senior Forward Deployment Engineer who embeds within customer 5G/6G/NTN development programs as a software developer, systems engineer, and deployment lead. Owns complex deployment issues across the protocol stack (Layer 1–3), writes and modifies production software and firmware, develops Python APIs, builds automation workflows, and serves as the technical bridge between Keysight and customer engineering teams.…See more Requires 6–7 years of software/systems engineering experience, deep expertise in at least one wireless protocol domain (PHY/L1, MAC/L2, or RRC/NAS/L3), proficiency in C/C++ and Python, Linux, embedded/real-time software, and hands-on debugging of protocol interactions through logs, traces, and packet captures.

Senior ASIC engineer responsible for defining, modeling, designing (digital and/or analog), optimizing, verifying, validating, implementing, and documenting IP blocks and SoCs for high-performance, low-power products. Design and architecture duties span RTL-to-GDS flow, circuit specifications, logic design, system simulation, timing, power analysis, and design verification.…See more Requires 2+ years of ASIC design/verification experience (or equivalent with advanced degree) and proficiency with EDA tools, scripting, and design verification methodologies. Works independently with cross-functional collaboration and produces detailed technical documentation.

As an ASIC RTL Design Engineer, you will define, model, design, optimize, verify, and validate IP blocks and SoCs for high-performance, low-power products. You will assist in creating architectures, circuit specifications, and logic designs based on system-level requirements, and collaborate with cross-functional teams to develop implementation strategies.…See more The role involves using EDA tools and RTL-to-GDS flows to execute design and supporting the evaluation of process flow from synthesis through place-and-route. You will work under supervision on tasks requiring multiple steps, planning, and problem-solving to deliver technical documentation for ASIC projects.

An Advanced Forward Deployment Engineer at Keysight embeds directly within customer wireless development environments as a software developer, systems engineer, and deployment lead. The role requires independently diagnosing and resolving complex deployment issues across protocol layers (L1–L3), writing and modifying application and protocol-stack software in C/C++ and Python, and delivering production-quality code and controlled releases.…See more You will analyze signaling flows and performance data, develop Python APIs and automation workflows, create diagnostic instrumentation, and act as a feedback loop between field problems and core product teams.

As an ASIC Digital Design Engineer, you will define, model, design, optimize, verify, and validate IP blocks and SoCs for high-performance, low-power memory subsystems (HBM, LPDDR). You'll work with cross-functional teams to develop architectures, circuit specifications, and logic designs based on system requirements, using EDA tools to execute the RTL-to-GDS flow and custom circuit design workflows.…See more Responsibilities include creating system simulations, evaluating implementation strategies, and documenting technical specifications for ASIC projects.

Design and optimize Network-on-Chip (NoC) architectures for high-performance Qualcomm SoCs with focus on physical implementation and PPA (power, performance, area) goals. Responsibilities include floorplan-driven architecture design, physical-aware synthesis strategies, clock tree planning, power analysis, timing closure, and custom placement/routing techniques.…See more Requires deep expertise in ASIC physical design, NoC protocols (AMBA, cache coherency), and scripting in Python, Perl, TCL, and C to analyze and optimize latency, area, performance, and power metrics.

As a Camera Firmware Engineer at Qualcomm, you will define, model, design, optimize, verify, validate, implement, and document IP blocks and SoCs for high-performance camera systems. You will assist in creating architectures, circuit specifications, logic designs, and system simulations based on system-level requirements, collaborating with cross-functional teams.…See more The role requires hands-on use of ASIC design tools (RTL to GDS flow, Virtuoso) and evaluation of the design flow from high-level design through synthesis, place and route, timing, and power analysis. You will write technical documentation and support the development of implementation strategies that meet system and customer requirements.

As a NoC Interconnect Design Engineer and Architect at Qualcomm, you will define, model, design, optimize, and verify network-on-chip IP blocks and SoCs for high-performance, low-power products. You will create architectures and circuit specifications based on system requirements, support the RTL-to-GDS implementation flow, and collaborate with cross-functional teams to meet customer needs.…See more The role requires hands-on use of EDA tools (RTL synthesis, place-and-route, timing/power analysis, and custom design tools like Virtuoso) and technical documentation. You will work under supervision on digital and/or analog design tasks that span from high-level specification through physical implementation.