floorplanning jobs in San Diego

Design and optimize Network-on-Chip (NoC) architectures for high-performance Qualcomm SoCs with focus on physical implementation and PPA (power, performance, area) goals. Responsibilities include floorplan-driven architecture design, physical-aware synthesis strategies, clock tree planning, power analysis, timing closure, and custom placement/routing techniques.…See more Requires deep expertise in ASIC physical design, NoC protocols (AMBA, cache coherency), and scripting in Python, Perl, TCL, and C to analyze and optimize latency, area, performance, and power metrics.

Staff Engineer role focused on CPU design, RTL development, and physical design for next-generation high-performance, low-power SoCs. Responsibilities span microarchitecture definition, Verilog/SystemVerilog RTL coding, synthesis, physical implementation (floorplanning, placement, routing, timing closure), and PPA optimization.…See more Will collaborate across architecture, verification, DFT, and post-silicon teams, and develop automation scripts in Python, Tcl, Perl, or Shell. Requires 4–10 years in ASIC/SoC, CPU, RTL, or physical design, strong digital design fundamentals, and hands-on experience with CPU microarchitecture and design closure flows.