low-power-design jobs in San Diego

Senior systems software engineer focused on power optimization for Snapdragon mobile SoCs. The role spans hardware-software integration across firmware, Linux kernel, and Android, requiring expertise in low-power design, DVFS, scheduler optimization, and post-silicon power debugging.…See more Responsibilities include prototyping power features from pre-silicon through productization, executing power KPI optimization across real workloads, and building power telemetry and analysis infrastructure. Strong foundation in computer architecture, embedded systems, and OS fundamentals required; hands-on firmware and Linux kernel development experience essential.

Qualcomm seeks a Senior System Software Engineer to optimize power efficiency across Snapdragon mobile SoCs. The role spans the full lifecycle from architecture and modeling through post-silicon debug, validation, and productization, requiring expertise in firmware, Linux kernel, and system software optimization.…See more Responsibilities include driving end-to-end power optimization across hardware/software boundaries, owning post-silicon power KPI execution, performing trade-off analysis on scheduler and DVFS algorithms, and developing power debug and automation infrastructure. The position demands strong embedded software development experience, deep understanding of computer architecture and OS fundamentals, and hands-on work with firmware and kernel-level tuning.

Qualcomm seeks a Systems Software Power Engineer to optimize power efficiency across Snapdragon mobile SoCs. The role spans the full lifecycle from architecture and design through post-silicon debug, validation, and productization, requiring deep expertise in power architectures, control loops, and low-power techniques.…See more The engineer will prototype and evaluate power features using pre-silicon platforms and post-silicon bring-up, perform trade-off analysis on scheduler and DVFS algorithms, and develop firmware, Linux kernel, and system-level optimizations. The position demands hands-on embedded software development, Linux kernel experience, computer architecture fundamentals, and electrical engineering knowledge of low-power design principles.

Design RTL for high-performance Hexagon/NPU processor cores used in mobile SoCs, servers, IoT, and automotive applications. Work across the full ASIC design flow from RTL through GDS2, collaborating with architecture, physical design, and verification teams on timing closure, power optimization, and area reduction.…See more Develop SystemVerilog RTL, run frontend design tools (linting, CDC, LEC, CLP), and support hardware integration and design verification. Requires 2+ years of practical RTL development experience with microprocessor design knowledge.

Staff Engineer role focused on CPU design, RTL development, and physical design for next-generation high-performance, low-power SoCs. Responsibilities span microarchitecture definition, Verilog/SystemVerilog RTL coding, synthesis, physical implementation (floorplanning, placement, routing, timing closure), and PPA optimization.…See more Will collaborate across architecture, verification, DFT, and post-silicon teams, and develop automation scripts in Python, Tcl, Perl, or Shell. Requires 4–10 years in ASIC/SoC, CPU, RTL, or physical design, strong digital design fundamentals, and hands-on experience with CPU microarchitecture and design closure flows.

Develop prototype AI/ML solutions for ASIC design automation at NXP, exploring state-of-the-art techniques like GenAI, reinforcement learning, graph neural networks, and CNNs to improve VLSI CAD workflows. The role involves collaborating with architecture, IP, and SoC design teams to evaluate and pilot automation applications on leading-edge semiconductor technologies.…See more Candidates must have 5+ years of AI/ML expertise, strong Python/C++ programming skills, and hands-on experience with Unix/Linux, Git, and software development tools. Understanding of VLSI design constraints, EDA tools, and physical design flows is highly desirable.

Lead Arm's SoC interconnect technology team as a senior architect with 15+ years of experience designing large-scale SoCs. Own performance modeling, microarchitecture, RTL design, and verification strategy for interconnect IP; drive adoption of industry standards (AMBA AXI/ACE/CHI, etc.) across CPU, GPU, NPU, and memory subsystems.…See more Mentor a team of architects and engineers while leading complex projects to tape-out, with expertise in coherent protocols, cache coherency, latency/bandwidth/power optimization, and system-level debug.

Head of Silicon Systems and Architecture role leading Google's XR silicon strategy and roadmap. Responsibilities include defining multi-year silicon architecture across main processors, co-processors, and connectivity; architecting split-compute topologies for low-latency offloading; optimizing perception and GenAI workloads for edge computing; and bridging technical alignment between Core Tech, Platform SW, Hardware, and external chipset vendors.…See more Requires 8+ years in silicon engineering, system integration, and hardware design; 5+ years in technical leadership with direct reports; and proven success shipping consumer electronics to mass production.

Design and verify Digital Signal Processor (DSP) architectures for Qualcomm's mobile, machine learning, automotive, and IoT products. Develop small to complex hardware blocks independently, applying high-performance microprocessor design concepts including multi-core, multi-threaded, and low-power optimization.…See more Conduct design verification, performance analysis, and architecture tradeoff evaluation using simulators, emulators, and synthesis tools. Collaborate with cross-functional teams to ensure designs meet specifications for performance, power, and timing while staying current with industry trends in machine learning and modem technologies.

Qualcomm seeks a Systems Software Power Engineer to optimize power efficiency for next-generation Snapdragon SoCs. The role spans the full lifecycle from pre-silicon modeling through post-silicon debug, requiring expertise in power architectures, control loops, and low-power techniques across hardware and software layers.…See more Key responsibilities include driving end-to-end power optimization across architecture, firmware, kernel, and Android teams; prototyping and evaluating power features; executing post-silicon power KPI validation; and developing power debug and analysis infrastructure. The position demands strong embedded software skills with hands-on experience in firmware and Linux kernel development, plus solid understanding of computer architecture, memory hierarchies, CPU/GPU design, and OS fundamentals.

Design, implement, and optimize real-time embedded modem firmware across protocol layers and drivers while meeting strict latency, memory, and power constraints. Pioneer AI-native development practices by integrating AI coding agents, LLM-based code review, and automated test synthesis into daily workflows to accelerate delivery and debugging.…See more Own end-to-end feature delivery from requirements through on-target bring-up, and debug complex multi-layer hardware issues using AI-assisted analysis. Requires deep expertise in modern C/C++, embedded systems (DSP/Arm architectures), RTOS internals, data structures, and hands-on target hardware debugging, combined with practical experience using AI coding assistants and agentic tools.