timing-closure jobs in San Diego

Senior ASIC design engineer role focused on next-generation high-speed HBM, LPDDR, and DDR memory subsystem architecture and RTL implementation for Qualcomm products. Responsibilities include developing memory controller and NoC-based subsystem specifications, RTL coding, micro-architecture design, synthesis, timing closure, physical design support, and gate-level simulation.…See more The role requires 5+ years of ASIC/RTL design experience, 3+ years of hardware architecture experience, and expertise in high-speed digital design (1GHz+) interfacing with CPU, GPU, DSP, and multimedia processors.

Design and develop uniform global methodologies for emulation build generation and debug across FPGA-based emulation platforms at Qualcomm's SoC digital hardware organization. Collaborate with architects, designers, verification engineers, and software teams to support pre-silicon prototyping and bring-up of new SoC designs.…See more Debug low-level software and hardware issues using tools like JTAG and kernel debuggers, with expertise in Verilog/SystemVerilog, FPGA platforms (Xilinx/Intel), and scripting languages. Requires 4+ years of ASIC design, verification, validation, or integration experience, with preferred 5+ years in emulation and silicon environments.

Design, develop, integrate, and test VHDL-based digital designs for software-defined radio applications, working with FPGA programming tools and multi-disciplinary teams. Analyze system requirements and design documents to resolve functional, performance, and timing issues in firmware codebases.…See more Requires hands-on experience in VHDL design, knowledge of communication protocols (I2C, SPI, UART, PCIe, Ethernet), and familiarity with EDA tools and FPGA device families. Must hold or be able to obtain an active Secret clearance.

Staff Engineer role focused on CPU design, RTL development, and physical design for next-generation high-performance, low-power SoCs. Responsibilities span microarchitecture definition, Verilog/SystemVerilog RTL coding, synthesis, physical implementation (floorplanning, placement, routing, timing closure), and PPA optimization.…See more Will collaborate across architecture, verification, DFT, and post-silicon teams, and develop automation scripts in Python, Tcl, Perl, or Shell. Requires 4–10 years in ASIC/SoC, CPU, RTL, or physical design, strong digital design fundamentals, and hands-on experience with CPU microarchitecture and design closure flows.

Blue Origin seeks a Technical Program Manager to lead SoC (System-on-Chip) development programs from requirements through production. The role requires managing complex hardware and semiconductor programs across multiple lifecycle phases, coordinating with highly technical engineering teams, external suppliers, and IP providers.…See more Responsibilities include change management, build-versus-buy decisions, supplier strategy, scheduling, risk management, and translating between detailed technical execution and business objectives. The ideal candidate has 7+ years of technical program management experience, a strong background in IC/SoC development, analog/mixed-signal design, digital ASIC, RF systems, or satellite communications, plus demonstrated ability to lead through tapeout, silicon bring-up, qualification, and production ramp.