noc-network-on-chip jobs in San Diego

Lead end-to-end DDR validation for next-generation LPDDR5X/LPDDR6 memory subsystems on AI Accelerator and mobile platforms, spanning pre-silicon through post-silicon phases. Drive memory bring-up, performance validation, system stress testing, and debug across emulation, FPGA, and silicon platforms.…See more Develop validation strategies, automation, and regression infrastructure while partnering with architecture, design, firmware, and vendor teams to resolve DDR controller, PHY, and system-level issues. Require 5+ years of DDR/memory subsystem validation experience, deep knowledge of LPDDR architectures, DDR controllers/PHYs, memory training algorithms, and strong post-silicon debug skills with C/C++ proficiency.

The SOC Platform Architect will work with hardware designers to gather and analyze power estimation data for Qualcomm SoC infrastructure IPs (interconnect, system cache, memory controllers, MMU), identify architectural bottlenecks and bugs, and propose optimizations. The role requires deep ASIC design and computer architecture expertise, along with understanding of system-level design, hardware-software trade-offs, and complete silicon design flows.…See more The candidate will coordinate with domain leads to ensure robust infrastructure deployment aligned with product requirements. Required background: 7+ years ASIC design/verification (or 5+ with a master's degree).

Qualcomm seeks a Senior AI Performance Architect to design hardware accelerator architectures optimized for AI training at scale. The role involves analyzing GPU/accelerator architectures, defining computational blocks supporting multiple datatypes and precisions, architecting memory and scale-out systems, and codesigning hardware with software/LLM requirements.…See more Responsibilities include competitive analysis, performance modeling, and pre-silicon prediction for ML training workloads. The ideal candidate spans software architecture, algorithm development, kernel optimization, and hardware accelerator design.

As a NoC Interconnect Design Engineer and Architect at Qualcomm, you will define, model, design, optimize, and verify network-on-chip IP blocks and SoCs for high-performance, low-power products. You will create architectures and circuit specifications based on system requirements, support the RTL-to-GDS implementation flow, and collaborate with cross-functional teams to meet customer needs.…See more The role requires hands-on use of EDA tools (RTL synthesis, place-and-route, timing/power analysis, and custom design tools like Virtuoso) and technical documentation. You will work under supervision on digital and/or analog design tasks that span from high-level specification through physical implementation.

As a SOC Platform Architect at Qualcomm's ASIC Engineering group, you will define and architect platform infrastructure hardware IP components (NOC, System Cache, Memory Controllers, System MMU) for next-generation SoCs. You'll work with hardware architects to gather requirements, develop deployment specifications, and coordinate with domain leads to create robust infrastructure deployment plans based on product needs.…See more The role requires strong ASIC design and computer architecture expertise, system-level design understanding, and knowledge of HW-SW feature trade-offs across the complete silicon design flow.

Design and architect network-on-chip (NoC) interconnect components for Qualcomm SoCs, from specification through RTL delivery. Perform micro-architecture analysis, power and performance tradeoffs, and protocol compliance evaluation for bus interconnects.…See more Deliver RTL, support verification and silicon validation teams, and collaborate with software teams on interconnect deployment. Requires strong knowledge of bus protocols (AHB, AXI, CHI), ASIC design flows, VLSI fundamentals, and experience deploying IPs in large SoC projects.