debug-architecture jobs in San Diego

Design and architect RISC-V System-on-Chip (SoC) platforms, leveraging deep expertise in heterogeneous compute, interconnect, memory systems, security, and power management. Develop and improve analysis tools including functional/performance simulators and profilers using C++ and Python.…See more Apply systems engineering rigor to define SoC-level architectures across boot, debug, timebase management, and real-time control components. Candidates should have 4+ years of systems engineering or SoC/IP architecture experience and demonstrate proficiency in behavioral/performance modeling and analytical techniques.

The SOC Platform Architect will work with hardware designers to gather and analyze power estimation data for Qualcomm SoC infrastructure IPs (interconnect, system cache, memory controllers, MMU), identify architectural bottlenecks and bugs, and propose optimizations. The role requires deep ASIC design and computer architecture expertise, along with understanding of system-level design, hardware-software trade-offs, and complete silicon design flows.…See more The candidate will coordinate with domain leads to ensure robust infrastructure deployment aligned with product requirements. Required background: 7+ years ASIC design/verification (or 5+ with a master's degree).

As a SOC Platform Architect at Qualcomm's ASIC Engineering group, you will define and architect platform infrastructure hardware IP components (NOC, System Cache, Memory Controllers, System MMU) for next-generation SoCs. You'll work with hardware architects to gather requirements, develop deployment specifications, and coordinate with domain leads to create robust infrastructure deployment plans based on product needs.…See more The role requires strong ASIC design and computer architecture expertise, system-level design understanding, and knowledge of HW-SW feature trade-offs across the complete silicon design flow.

Define and architect next-generation SoC infrastructure hardware components including interconnect (NoC), system cache, memory controllers, and system MMU for Qualcomm SoCs. The role requires deep expertise in multi-die/chiplet architectures, industry-standard protocols (PCIe, CXL, USB, UFS, MIPI, UCIe), and HW-SW interfaces to create developer-friendly designs.…See more Responsibilities include performance modeling, RTL design flow understanding, and trade-off analysis across quality of service, power management, security, and debug features. The position demands 4+ years of systems engineering or architecture experience with a degree in electrical engineering or computer science.