rtl-verification jobs in San Diego

Senior ASIC design engineer role focused on next-generation high-speed HBM, LPDDR, and DDR memory subsystem architecture and RTL implementation for Qualcomm products. Responsibilities include developing memory controller and NoC-based subsystem specifications, RTL coding, micro-architecture design, synthesis, timing closure, physical design support, and gate-level simulation.…See more The role requires 5+ years of ASIC/RTL design experience, 3+ years of hardware architecture experience, and expertise in high-speed digital design (1GHz+) interfacing with CPU, GPU, DSP, and multimedia processors.

Design and develop performance modeling platforms and tools for Qualcomm's AI/ML hardware accelerators targeting cloud data server applications. Analyze and optimize LLM and AI workloads on SoC architectures, working across hardware architecture, DDR memory controllers, NoC design, and compiler frameworks.…See more Collaborate with multi-disciplinary hardware and systems engineers to find optimal architecture tradeoffs and improve performance and power efficiency. Apply deep expertise in AI workloads, ML frameworks, computer architecture, and RTL design/verification to build systems that validate LLMs and complex ML networks.

As a CPU SoC Verification Engineer at Google, you will drive ARM-based SoC verification from RTL simulation through post-silicon debug, ensuring functional integrity of CPU subsystems. You will develop robust verification environments, execute Gate Level Simulation (GLS) and timing-annotated workflows, and partner with ATE teams to diagnose hardware failures and stabilize production patterns.…See more The role requires 4+ years of ARM SoC verification experience including cache coherency, NoC interconnects, high-speed bus protocols, and PVT corner analysis. You will translate simulation sequences into production-ready formats and debug complex hardware failures in both virtual and physical silicon environments.

As a CPU SoC Verification Engineer, you will drive ARM-based SoC verification from RTL simulation through post-silicon debug, ensuring functional integrity of CPU subsystems. You'll develop robust verification environments, execute Gate Level Simulation (GLS) and timing-annotated simulations, and lead debug efforts to diagnose hardware failures and stabilize high-speed patterns in production.…See more The role requires expertise in RTL verification, cache coherency, Network-on-Chip interconnects, and high-speed bus protocols, with experience translating simulation sequences into ATE-ready formats using industry-standard EDA tools.