post-silicon-debug jobs in San Diego

Design and architect network-on-chip (NoC) interconnect components for Qualcomm SoCs, from specification through RTL delivery. Perform micro-architecture analysis, power and performance tradeoffs, and protocol compliance evaluation for bus interconnects.…See more Deliver RTL, support verification and silicon validation teams, and collaborate with software teams on interconnect deployment. Requires strong knowledge of bus protocols (AHB, AXI, CHI), ASIC design flows, VLSI fundamentals, and experience deploying IPs in large SoC projects.

Qualcomm seeks a Systems Software Power Engineer to optimize power efficiency for next-generation Snapdragon SoCs. The role spans the full lifecycle from pre-silicon modeling through post-silicon debug, requiring expertise in power architectures, control loops, and low-power techniques across hardware and software layers.…See more Key responsibilities include driving end-to-end power optimization across architecture, firmware, kernel, and Android teams; prototyping and evaluating power features; executing post-silicon power KPI validation; and developing power debug and analysis infrastructure. The position demands strong embedded software skills with hands-on experience in firmware and Linux kernel development, plus solid understanding of computer architecture, memory hierarchies, CPU/GPU design, and OS fundamentals.

Qualcomm seeks a Sr. Staff/Principal Software Engineer to provide system-level technical leadership for next-generation ARM server platforms, spanning Linux kernel, firmware, and platform software.…See more The role requires architecting across hardware, firmware, OS, and hypervisor boundaries using standards like ACPI, UEFI, SystemReady, SBSA/SBBR, and PSCI. Responsibilities include Linux kernel enablement, performance optimization, platform driver development, and guiding boot flows, power management, virtualization, and telemetry. This position demands 10+ years of hands-on Linux kernel development, deep C/assembly proficiency, firmware and pre/post-silicon debug experience, and the ability to mentor senior engineers while influencing SoC roadmaps.