noc jobs in San Diego

Lead system-level validation strategy, planning, and content development for next-generation premium mobile and AI accelerator SoCs across emulation and silicon phases. Own end-to-end validation roadmaps, test coverage plans, and cross-domain content execution while partnering with architecture, design, firmware, and software teams.…See more Manage geographically distributed engineering teams, drive root-cause analysis on critical silicon and software issues, and champion AI/GenAI-driven validation methodologies. Requires 8+ years in SoC validation, strong understanding of modern SoC architectures (CPUs, memory subsystems, interconnects, power management, security), and demonstrated technical leadership.

Lead system-level validation strategy, planning, and execution for next-generation premium mobile and AI accelerator SoCs at Qualcomm. Own end-to-end validation content across pre-silicon (emulation, FPGA) and post-silicon (silicon) phases, partnering with architecture, design, DV, firmware, and software teams to ensure comprehensive coverage.…See more Direct geographically distributed engineering teams, drive content quality and scalability, debug complex silicon and firmware issues, and champion AI/GenAI-driven validation methodologies. Requires 8+ years of SoC validation experience, deep knowledge of modern SoC architectures (ARM CPUs, DDR/HBM, NoC, power management, security), and proven technical leadership.

Design and architect RISC-V System-on-Chip (SoC) platforms, leveraging deep expertise in heterogeneous compute, interconnect, memory systems, security, and power management. Develop and improve analysis tools including functional/performance simulators and profilers using C++ and Python.…See more Apply systems engineering rigor to define SoC-level architectures across boot, debug, timebase management, and real-time control components. Candidates should have 4+ years of systems engineering or SoC/IP architecture experience and demonstrate proficiency in behavioral/performance modeling and analytical techniques.

Design and architect safety mechanisms for system-on-chip (SoC) platforms across Qualcomm's product portfolio. Collaborate with hardware design, verification, software, and product teams to develop SoC-wide safety solutions that meet automotive and industrial safety standards.…See more Conduct workload analysis, prototype system solutions, and provide quantitative justification for architectural directions using simulators and profilers. Analyze failure modes, decompose complex safety use cases, and make safety recommendations to design and engineering teams.

Design and develop uniform global methodologies for emulation build generation and debug across FPGA-based emulation platforms at Qualcomm's SoC digital hardware organization. Collaborate with architects, designers, verification engineers, and software teams to support pre-silicon prototyping and bring-up of new SoC designs.…See more Debug low-level software and hardware issues using tools like JTAG and kernel debuggers, with expertise in Verilog/SystemVerilog, FPGA platforms (Xilinx/Intel), and scripting languages. Requires 4+ years of ASIC design, verification, validation, or integration experience, with preferred 5+ years in emulation and silicon environments.

Design and optimize Network-on-Chip (NoC) architectures for high-performance Qualcomm SoCs with focus on physical implementation and PPA (power, performance, area) goals. Responsibilities include floorplan-driven architecture design, physical-aware synthesis strategies, clock tree planning, power analysis, timing closure, and custom placement/routing techniques.…See more Requires deep expertise in ASIC physical design, NoC protocols (AMBA, cache coherency), and scripting in Python, Perl, TCL, and C to analyze and optimize latency, area, performance, and power metrics.

Lead Arm's SoC interconnect technology team as a senior architect with 15+ years of experience designing large-scale SoCs. Own performance modeling, microarchitecture, RTL design, and verification strategy for interconnect IP; drive adoption of industry standards (AMBA AXI/ACE/CHI, etc.) across CPU, GPU, NPU, and memory subsystems.…See more Mentor a team of architects and engineers while leading complex projects to tape-out, with expertise in coherent protocols, cache coherency, latency/bandwidth/power optimization, and system-level debug.

Define and architect next-generation SoC infrastructure hardware components including interconnect (NoC), system cache, memory controllers, and system MMU for Qualcomm SoCs. The role requires deep expertise in multi-die/chiplet architectures, industry-standard protocols (PCIe, CXL, USB, UFS, MIPI, UCIe), and HW-SW interfaces to create developer-friendly designs.…See more Responsibilities include performance modeling, RTL design flow understanding, and trade-off analysis across quality of service, power management, security, and debug features. The position demands 4+ years of systems engineering or architecture experience with a degree in electrical engineering or computer science.