Principal-level verification engineer responsible for designing and validating modem PHY IP, including OFDM, synchronization, channel estimation, FEC, MIMO, and beamforming. Will develop constrained-random and directed test strategies using SystemVerilog and UVM, correlate RTL behavior against reference models, define coverage metrics, and support FPGA prototyping and post-silicon debug.… Requires 10+ years in digital design verification or modem/baseband verification, with deep expertise in DSP signal processing, fixed-point quantization, and complex communications systems.
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