power-domain-analysis jobs in San Diego

Design and optimize Network-on-Chip (NoC) architectures for high-performance Qualcomm SoCs with focus on physical implementation and PPA (power, performance, area) goals. Responsibilities include floorplan-driven architecture design, physical-aware synthesis strategies, clock tree planning, power analysis, timing closure, and custom placement/routing techniques.…See more Requires deep expertise in ASIC physical design, NoC protocols (AMBA, cache coherency), and scripting in Python, Perl, TCL, and C to analyze and optimize latency, area, performance, and power metrics.