Lead end-to-end DDR validation for next-generation LPDDR5X/LPDDR6 memory subsystems on AI Accelerator and mobile platforms, spanning pre-silicon through post-silicon phases. Drive memory bring-up, performance validation, system stress testing, and debug across emulation, FPGA, and silicon platforms.… Develop validation strategies, automation, and regression infrastructure while partnering with architecture, design, firmware, and vendor teams to resolve DDR controller, PHY, and system-level issues. Require 5+ years of DDR/memory subsystem validation experience, deep knowledge of LPDDR architectures, DDR controllers/PHYs, memory training algorithms, and strong post-silicon debug skills with C/C++ proficiency.
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