latency-optimization jobs in San Diego

Lead Arm's SoC interconnect technology team as a senior architect with 15+ years of experience designing large-scale SoCs. Own performance modeling, microarchitecture, RTL design, and verification strategy for interconnect IP; drive adoption of industry standards (AMBA AXI/ACE/CHI, etc.) across CPU, GPU, NPU, and memory subsystems.…See more Mentor a team of architects and engineers while leading complex projects to tape-out, with expertise in coherent protocols, cache coherency, latency/bandwidth/power optimization, and system-level debug.

Staff engineer leading architecture and evolution of Qualcomm's Ambient Perception Platform for always-on, context-aware AI on power-constrained edge devices. Responsibilities include designing low-power AI runtime platforms, multimodal sensing systems, secure data architectures, and heterogeneous computing frameworks across Android, Linux, Windows, XR, automotive, and IoT.…See more Requires 4+ years software engineering experience (or equivalent with advanced degree), 2+ years with C, C++, Java, or Python, and expertise in embedded systems, ARM/DSP/NPU optimization, and edge AI workload efficiency. Strong preference for 8–12+ years in software architecture, platform frameworks, and heterogeneous SoC development.