Sr. Staff Reliability Engineer
Embedded SystemsSoftware Development2 5d 3d IntegrationBackside Power DeliveryBti Bias Temperature InstabilityChiplet ArchitecturesCmos Technology NodesDevice PhysicsElectromigrationFailure Mechanism AnalysisFinfetGaa Gate All AroundHci Hot Carrier InjectionInterconnect ReliabilityMol Beol Wear OutReliability TestingSelf HeatingSemiconductor QualificationTddb Time Dependent Dielectric BreakdownTest StructuresTsv Through Silicon Via
San DiegoLast seen 1 day ago
Summary
Sr. Staff Reliability Engineer at Qualcomm leads semiconductor reliability strategy for advanced CMOS nodes (FinFET, GAA) and complex SoCs. The role requires deep expertise in device and interconnect failure physics—BTI, TDDB, HCI, electromigration, self-heating—and advanced packaging architectures (2.5D/3D, TSV, chiplets). Responsibilities include defining foundry qualification requirements, performing wear-out and aging analysis, identifying lifecycle risks, and establishing scalable reliability processes. The engineer mentors the organization, provides expert judgment on critical trade-offs, and communicates reliability status and strategic recommendations to senior leadership.